Light Emitting Device

ABSTRACT

Power consumption required for charging and discharging a source signal line is reduced in an active matrix EL display device. A bipolar transistor (Bi 1 ) has a base terminal B connected to an output terminal c 1  of an operational amplifier (OP 1 ), a collector terminal C connected to a low power potential (GND), and an emitter terminal E connected to a resistor R 2 . A high power potential (VBH) is a potential in synchronization with a high power potential of a light emitting element. A potential of the output terminal c 1  of the operational amplifier (OP 1 ) is outputted as a buffer low power potential (VBL). The low power potential (VBL) corresponds to a potential difference between the high power potential (VBH) and a high power potential (V 1 ). Accordingly, the low power potential (VBL) can follow the high power potential (VBH), that is a high power potential of the light emitting element.

TECHNICAL FIELD

The invention relates to a light emitting device provided with a lightemitting element.

BACKGROUND ART

Research on an active matrix light emitting device having aself-luminous element has been becoming more active. A typical exampleof such a self-luminous device is an EL display device.

In recent years, a flat panel display device which is widely used for adisplay portion of a portable information terminal as well as for amedium-size or a large-size display device has the increasing number ofpixels in accordance with the high resolution. In accordance with theincrease in the number of pixels, these displays employ pixels in anactive matrix structure which has a thin film transistor (TFT) in eachpixel and can store image data.

There are an analog gray scale method and a digital gray scale method ina gray scale method of an active matrix EL display device. The digitalgray scale method has a time gray scale method, an area gray scalemethod, a method in which the time gray scale method and the area grayscale method are mixed, and the like. In either of the time gray scalemethod and the area gray scale method of the digital gray scale method,each pixel or subpixel is driven by binary values, namely an on stateand an off state.

Accordingly, there is an advantage in that deterioration of imagequality due to variations in a threshold voltage Vth of thin filmtransistors (TFTs) arranged in the pixel can be reduced as compared tothe analog gray scale method. Patent Document 1 discloses a digital grayscale display performed by the time gray scale method.

Further, it is preferable for rapidly writing video signals to each of aplurality of pixels to employ a line sequential method in which data isinputted simultaneously per one row. Description is made with referenceto FIG. 9 on an active matrix EL display device driven by the linesequential method to perform the digital gray scale display.

FIG. 9 shows a configuration of a display device driven by the digitalgray scale method in which binary data is inputted to pixels in theactive matrix structure. A pixel portion 501 includes a light emittingelement typified by an EL element and a TFT for controlling lightemission of the light emitting element. A source signal line drivercircuit 502 including a shift register 504, a first latch circuit 505, asecond latch circuit 506, a level shifter 507, and a buffer groupcircuit 508, and a gate signal line driver circuit 503 including a shiftregister 509, a level shifter 510, and a buffer group circuit 511 arearranged in the periphery of the pixel portion 501. FIGS. 10A and 10Bshow equivalent circuits of the buffer group circuit 508.

As shown in FIG. 10A, the buffer group circuit 508 includes a pluralityof buffers 601 provided in each column. FIG. 10B shows an equivalentcircuit of the buffer 601 which is formed of two inverters. An input ofthe buffer 601 is connected to the level shifter 507 and an outputthereof is connected to the pixel portion 501. Further, a buffer highpower potential (VBH) is applied from a signal line 602 and a low powerpotential (VBL) is applied from a signal line 603.

Description is made on a method for driving the active matrix displaydevice shown in FIG. 9 by the line sequential method to perform adigital gray scale display. First, the shift register 509 outputs aselection pulse sequentially from a first stage in accordance with aclock signal (GCK) and a start pulse (GSP). After that, amplitudeconversion is carried out by the level shifter 510, thereby gate linesare sequentially selected from the first row by the buffer group circuit511.

In the selected row, the shift register 504 sequentially outputssampling pulses from a first stage in accordance with a clock signal(SCK) and a start pulse. The first latch circuit 505 captures videosignals (Video) at timing that sampling pulses are inputted. The videosignals captured in each stage are held in the first latch circuit 505.

When a latch pulse (LAT) is inputted after video signals of one row areall captured, the video signals held in the first latch circuit 505 aretransferred to the second latch circuit 506 all at once, thereby allsource signals are charged and discharged.

At this time, the buffer high power potential (VBH) which charges anddischarges the source signal line is in synchronization with a lightemitting element high power potential (ANODE) while the low powerpotential (VBL) is fixed. In this specification, the light emittingelement high power potential (ANODE) corresponds to a potential appliedto an anode of the light emitting element.

The aforementioned operations are repeated from the first to the lastrows, and thus data is written to all the pixels. Accordingly, an imagecorresponding to one frame is displayed. Similar operations are repeatedto display images.

-   -   [Patent Document 1]    -   Japanese Patent Application Laid-Open no. 2001-5426

DISCLOSURE OF INVENTION

In the analog gray scale method, a gray scale display can be performedby writing data to the source signal line at least once in one frame.

On the contrary, in the digital gray scale method such as the time grayscale method in which each pixel is driven by binary values of the onstate and the off state, the area gray scale method, and the method inwhich the time gray scale method and the area gray scale method aremixed, data is required to be written to the source signal line aplurality of times in one frame to display gray scales.

In an EL display device, a source signal line is a load for a bufferbecause of a plurality of TFTs provided in a pixel portion and parasiticcapacitance. When data written to the source signal line changes from aLow potential to a High potential in the digital gray scale method, anexternal high potential power source which applies a high powerpotential (VBH) charges the load capacitance due to the source signalline from a Low potential to a High potential through a p-channel TFT ofthe buffer 601. On the other hand, when data written to the sourcesignal line changes from a High potential to a Low potential, anexternal low potential power source which applies a low power potential(VBL) discharges the charges from the load capacitance due to the sourcesignal line from a High potential to a Low potential through ann-channel TFT of the buffer 601.

These power are consumed when a voltage of the source signal linechanges. Therefore, when an output of the source signal line oftenchanges, power consumption of the external power source increases.Accordingly, in the digital gray scale method, power consumption of theexternal power source increases when displaying an image which requiresa large number of gray scale levels such as a natural image and an imagein which logic is frequently inversed per one row such as a 1-dotchecker (here, light emission pixels and non-light emission pixels arealternately arranged in an active matrix structure), as a potential ofthe source signal line frequently changes.

Further, the current value to a light emitting element of a pixelportion also depends on a temperature. In particular, in the case ofusing an organic compound for a light emitting element, temperaturecharacteristics are significant. Even when the same voltage is appliedbetween electrodes of an EL element, more current flows through the ELelement as the temperature rises because of the temperaturecharacteristics of the EL element. Therefore, a display device consumesmore power as the temperature of the EL element rises, which increasesluminance of a light emitting element.

In the case of a color display, the light emitting element high powerpotential (ANODE) is set at different levels for each EL elementdepending on the light emitting material. In an EL element which emitsred (R) light, an EL element which emits green (G) light, and an ELelement which emits blue (B) light, the characteristics thereof changesdifferently due to deterioration over time and temperature.

In addition, for example, in the case where a user displays redfrequently, only the EL element of R deteriorates prior to the other ELelements. Therefore, a display device which can manage various potentialchanges of the light emitting element high power potential (ANODE) isdemanded.

A buffer high power potential (VBH) is required to be equal to or higherthan the light emitting element high power potential (ANODE). The bufferhigh power potential (VBH) charges the source signal line, therefore,less power is required for the buffer high power potential (VBH) as thepotential to be charged is lower. Therefore, the buffer high powerpotential (VBH) is preferably equal to the light emitting element highpower potential (ANODE).

As described above, the light emitting element high power potential(ANODE) changes depending on a deterioration over time, a temperaturechange, a frequency of use, and the like. Accordingly, the buffer highpower potential (VBH) is required to follow the light emitting elementhigh power potential (ANODE) and to be in synchronization with the lightemitting element high power potential (ANODE) in order to reduce thepower required for charging at the desired light emitting element highpower potential (ANODE).

Accordingly, the buffer high power potential (VBH) which charges anddischarges the source signal line in a conventional display device is insynchronization with the light emitting element high power potential(ANODE) while the low power potential (VBL) is fixed.

As a result, a conventional buffer circuit tends to consume more poweras described above, which easily rises the temperature of the buffer. Inaccordance with the generated heat of the buffer, a temperaturedistribution occurs in a pixel portion, leading to variations inluminance.

Alternatively, the light emitting element high power potential (ANODE)rises due to a deterioration over time and a temperature rise of an ELelement, which results in increasing a potential difference to chargeand discharge the source signal line, that is a difference between thehigh power potential (VBH) and the low power potential (VBL).Accordingly, the buffer 601 to charge and discharge the source signalline consumes more power and thus generates heat. As a result,variations in luminance of a pixel portion occur.

Accordingly, in the digital gray scale method, power consumptionrequired for writing data to the source signal line is a serious issuein a compact display device for a portable terminal which is required tobe low in power consumption. Further, it is hard to avoid the increasein parasitic capacitance of the source signal line in accordance withthe increase in size of a display device such as a television, and thereduction in power consumption is a problem similarly to a compactdisplay device.

The invention is made in view of the aforementioned problems so that acircuit using an inverter, such as a buffer consumes less power.Further, the invention is made to reduce power consumption required forcharging and discharging the source signal line of an active matrixdisplay device using a light emitting element.

According to the invention, a low power potential (VBL) of a buffer(inverter) which charges and discharges a source signal line follows ahigh power potential (VBH) thereof. In a light emitting device, inparticular, the low power potential (VBL) follows a light emittingelement high power potential (ANODE).

A light emitting device in accordance with the invention includes alight emitting element, a bipolar transistor, an operational amplifier,and first to fourth resistors. In the bipolar transistor, a baseterminal is connected to an output terminal of the operational amplifierand a collector terminal is connected to a low power potential. Thefirst resistor has one terminal connected to a first high powerpotential and the other terminal connected to a first input terminal ofthe operational amplifier. The second resistor has one terminalconnected to a first input terminal of the operational amplifier and theother terminal connected to an emitter terminal of the bipolartransistor. The third resistor has one terminal connected to a secondhigh power potential and the other terminal connected to a second inputterminal of the operational amplifier. The fourth resistor has oneterminal connected to a second input terminal of the operationalamplifier and the other terminal connected to the low power potential.The potentials at the emitter terminal of the bipolar transistor and atthe other terminal of the second resistor are supplied as a low powerpotential of a buffer of a driver circuit. The second high powerpotential is supplied as a high power potential of the buffer.

A light emitting device in accordance with the invention includes alight emitting element, an operational amplifier, and first to fourthresistors. The first resistor has one terminal connected to a first highpower potential and the other terminal connected to a first inputterminal of the operational amplifier. The second resistor has oneterminal connected to the first input terminal of the operationalamplifier and the other terminal connected to an output terminal of theoperational amplifier. The third resistor has one terminal connected toa second high power potential and the other terminal connected to asecond input terminal of the operational amplifier. The fourth resistorhas one terminal connected to the second input terminal of theoperational amplifier and the other terminal connected to a low powerpotential. A potential at the other terminal of the second resistor issupplied as a low power potential of a buffer and the second high powerpotential is supplied as a high power potential of the buffer.

According to the invention, a light emitting element of a light emittingdevice is arranged in a pixel. As the light emitting element, an ELelement is used. An EL element has a structure in which a pair ofelectrodes (an anode and a cathode) sandwich a layer (hereinafterreferred to as an EL layer) which generates electroluminescence when anelectric field is applied thereto. An EL layer is formed of an organiccompound and normally has a stacked-layer structure. Typically, astacked-layer structure of a hole transporting layer, a light emittinglayer, and an electron transporting layer is suggested.

Further, luminescence of the EL layer includes light emission(fluorescence) generated when returning from a singlet excitation stateto a ground state, and light emission (phosphorescence) generated whenreturning from a triplet excitation state to a ground state. A lightemitting device of the invention may employ one or both of theaforementioned light emission.

Besides, a structure in which a hole injecting layer, a holetransporting layer, a light emitting layer, and an electron transportinglayer are stacked over an anode in this order or a structure in which ahole injecting layer, a hole transporting layer, a light emitting layer,an electron transporting layer, and an electron injecting layer arestacked over an anode in this order may be employed as well. Aphosphorescent pigment and the like may be added to the light emittinglayer.

In this specification, all layers provided between a cathode and ananode are collectively referred to as an EL layer. Therefore, a holeinjecting layer, a hole transporting layer, a light emitting layer, anelectron transporting layer, an electron injecting layer and the likethat are described above are all included in the EL layer.

According to the invention, when a high power potential (VBH or ANODE)rises, a low power potential of a buffer rises by following the highpower potential. Therefore, a rise in a potential difference between thehigh power potential and the low power potential supplied to the buffer(inverter) can be suppressed. As a result, data of the source signalline can be rewritten by less power. Accordingly, heat generated by thebuffer can be suppressed, which can reduce variations in luminance ofthe pixel portion caused by the generated heat.

Accordingly, the invention is quite favorable for a light emittingdevice such as an EL display device which performs digital gray scaledrive by the line sequential method.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing Embodiment Mode 1.

FIGS. 2A and 2B are diagrams showing Embodiment Mode 1.

FIG. 3 is a diagram showing Embodiment Mode 2.

FIGS. 4A and 4B are diagrams showing Embodiment Mode 2.

FIG. 5 is a diagram showing a pixel portion of Embodiment 1.

FIG. 6 shows a buffer low power potential (VBL) in accordance with alight emitting element high power potential (ANODE).

FIG. 7 shows a current flowing through a signal line which supplies abuffer low power potential (VBL) in accordance with a light emittingelement high power potential (ANODE).

FIGS. 8A to 8D show temperature distribution of a source signal linedriver circuit and luminance distribution of a pixel portion inEmbodiment Mode 1 and a comparison example respectively.

FIG. 9 shows an EL display device of a digital gray scale method.

FIGS. 10A and 10B show equivalent circuits of a buffer.

FIGS. 11A to 11F are views showing electronic devices.

BEST MODE FOR CARRYING OUT THE INVENTION

Although the invention will be fully described by way of embodimentmodes and embodiment with reference to the accompanying drawings, it isto be understood that various changes and modifications will be apparentto those skilled in the art. Therefore, unless otherwise such changesand modifications depart from the scope of the invention, they should beconstrued as being included therein. Note that identical portions inembodiment modes are denoted by the same reference numerals and detaileddescriptions thereof are omitted.

EMBODIMENT MODE 1

This embodiment mode is described with reference to FIGS. 1, 2A, and 2B.

FIG. 1 is a circuit diagram of a potential generating circuit of thisembodiment mode. As shown in FIG. 1, the potential generating circuitincludes resistors R1 to R4, an operational amplifier (OP1) 1002, and abipolar transistor (Bi1) 1007.

Two power source connecting terminals of the operational amplifier OP1are inputted with a high power potential (VDD1) and a low powerpotential (GND) respectively. Further, an output terminal c1 of theoperational amplifier (OP1) is connected to a base terminal B of thebipolar transistor (Bi1). The base terminal B of the bipolar transistor(Bi1) is connected to the output terminal c1 of the operationalamplifier (OP1) and a collector terminal C thereof is connected to thelow power potential (GND).

The resistor R1 has one terminal connected to a high power potential(V1) and the other terminal connected to an input terminal al of theoperational amplifier (OP1). The resistor R2 has one terminal connectedto the input terminal al of the operational amplifier (OP1) and theother terminal connected to an emitter terminal E of the bipolartransistor (Bi1). The resistor R3 has one terminal connected to a highpower potential (VBH) and the other terminal connected to an inputterminal b1 of the operational amplifier (OP1). The resistor R4 has oneterminal connected to the input terminal b1 of the operational amplifier(OP1) and the other terminal connected to the low power potential (GND).Potentials at the emitter terminal E of the bipolar transistor (Bi1) andthe other terminal of the resistor R2 are outputted as a low powerpotential (VBL). The low power potential (VBL) corresponds to adifference between the high power potential (VBH) and the high powerpotential (V1).

FIG. 2A shows a light emitting device using the circuit shown in FIG. 1.In FIG. 2A, the same reference numerals as those in FIG. 9 denote thesame components.

In FIG. 2A, a pixel portion 501 is provided with a light emittingelement, which is typically an EL element, and a TFT for controllinglight emission of the light emitting element, thereby forming pixels inan active matrix structure. A source signal line driver circuit 502 anda gate signal line driver circuit 503 formed by using TFTs are arrangedin the periphery of the pixel portion 501 over the same substrate 500 asthe pixel portion 501.

The source signal line driver circuit 502 includes a shift register 504,a first latch circuit 505, a second latch circuit 506, a level shifter507, and a buffer group circuit 508. The gate signal line driver circuit503 includes a shift register 509, a level shifter 510, and a buffergroup circuit 511.

In FIG. 2A also, buffers 601 are arranged per column in the buffer groupcircuit 508 as shown in FIG. 10A. FIG. 10B shows an equivalent circuitof the buffer 601. The buffer group circuit 508 is connected to a signalline (a power source line) 1003 for supplying a buffer high powerpotential (VBH) and a signal line (a power source line) 1004 forsupplying a buffer low power potential (VBL). Further, the signal line1003 is connected to the signal line 602 which supplies the buffer highpower potential (VBH) of the buffer group circuit 508. The signal line1004 is connected to a signal line 603 which supplies the buffer lowpower potential (VBL) (see FIG. 10B). As a result, the buffer high powerpotential (VBH) is supplied from the signal line 1003 to the buffergroup circuit 508, and the low power potential (VBL) is supplied fromthe signal line 1004.

Further, a power supply line for supplying power to an anode of thelight emitting element is provided. The power supply line is connectedto an external power source which applies the buffer high powerpotential (VBH). Therefore, the buffer high power potential (VBH) isequal to the light emitting element high power potential (ANODE). It isto be noted that the high power potential (VBH) of the buffer and thelight emitting element high power potential (ANODE) may be at the samelevel or different external power sources may be provided. Sharing thepower source leads to the reduction in power and the number ofconnecting portions.

In this embodiment mode, the potential generating circuit shown in FIG.1 is connected to the signal line 1004. The potential generating circuitincludes, a circuit 1001 formed of the resistors R1 to R4 and anoperational amplifier (OP1) 1002, and a bipolar transistor (Bi1) 1007.In the light emitting device of this embodiment mode, the pixel portion501, the source signal line driver circuit 502, and the gate signal linedriver circuit 503 are formed by using TFTs over the same substrate 500except for the bipolar transistor (Bi1) 1007. The bipolar transistor(Bi1) 1007 is formed by using an IC chip and mounted over the substrate500, for example, by a COG method.

FIG. 2B shows a circuit diagram of the circuit 1001. Two power sourceconnecting terminals of the operational amplifier (OP1) 1002 areinputted with the high power potential (VDD1) and the low powerpotential (GND) respectively. Further, the base terminal B of thebipolar transistor (Bi1) 1007 is connected to the output terminal cl ofthe operational amplifier (OP1) 1002.

A base terminal B of the bipolar transistor (Bi1) 1007 is connected tothe output terminal c1 of the operational amplifier (OP1) 1002, acollector terminal C thereof is connected to the low power potential(GND), and an emitter terminal E thereof is connected to the resistor R2and the signal line 1004 which supplies the low power potential (VBL).

The resistor R1 has one terminal connected to a signal line (a powersource line) 1005 which supplies the high power potential (V1) and theother terminal connected to the input terminal al of the operationalamplifier (OP1) 1002. The resistor R2 has one terminal connected to theinput terminal al of the operational amplifier (OP1) 1002 and the otherterminal connected to the emitter terminal E of the bipolar transistor(Bi1) 1007. The resistor R3 has one terminal connected to the high powerpotential (VBH) of the buffer and the signal line 1003 which suppliesthe light emitting element high power potential (ANODE) and the otherterminal thereof connected to the input terminal b1 of the operationalamplifier (OP1) 1002. The resistor R4 has one terminal connected to theinput terminal b1 of the operational amplifier (OP1) 1002 and the otherterminal connected to the low power potential (GND).

The high power potential (V1) is at a lower level than the buffer highpower potential (VBH) and the light emitting element high powerpotential (ANODE). In this embodiment mode, the buffer high powerpotential (VBH) and the light emitting element high power potential(ANODE) are at the same level, however, the buffer high power potential(VBH) may be at a higher level. In this case, different external powersources are used for the light emitting element high power potential(ANODE) and the buffer high power potential (VBH).

In this embodiment mode, an amplifier ratio of the operational amplifier(OP1) 1002 is 1 and resistance of the resistors R1 to R4 are all equal.It is needless to say that the resistance of the resistors R1 to R4 maybe changed as required so as to set the buffer high power sourcepotential (VBH), the light emitting element high power potential(ANODE), the buffer low power potential (VBL), and the high powerpotential (V1) at the required levels. Further, the operationalamplifier (OP1) 1002 is preferably designed to consume less power.

By using the potential generating circuit formed of the operationalamplifier (OP1) 1002 of this embodiment mode, the buffer low powerpotential (VBL) becomes a potential obtained by subtracting the highpower potential (V1) from the light emitting element high powerpotential (ANODE).

Accordingly, the buffer low power potential (VBL) rises by following thelight emitting element high power potential (ANODE), thereby an increasein power consumption of the buffer can be suppressed.

In the potential generating circuit of this embodiment mode, the circuit1001 except for the bipolar transistor (Bi1) is formed over the samesubstrate as the pixel portion 501, the source signal line drivercircuit 502, and the gate signal line driver circuit 503, thereby thenumber of external components can be reduced. The potential generatingcircuit shown in FIG. 1 may be all formed of ICs which then may bemounted over the substrate 500, for example, by the COG method and thelike.

In this embodiment mode, the source signal line driver circuit 502 andthe gate signal line driver circuit 503 as well as the pixel portion 501are formed by using TFTs, however, a portion or all of each circuit maybe formed of an IC and then mounted by the COG method or a TAB method.

EMBODIMENT MODE 2

FIG. 3 is a circuit diagram of a potential generating circuit of thisembodiment mode. As shown in FIG. 3, the potential generating circuitincludes the resistors R1 to R4 and the operational amplifier (OP1).

Two power source connecting terminals of the operational amplifier (OP1)are inputted with the high power potential (VDD1) and the low powerpotential (GND) respectively.

The resistor R1 has one terminal connected to the high power potential(V1) and the other terminal connected to an input terminal al of anoperational amplifier (OP1) 1102. The resistor R2 has one terminalconnected to the input terminal a1 of the operational amplifier (OP1)1102 and the other terminal connected to an output terminal cl of theoperational amplifier (OP1) 1102. The resistor R3 has one terminalconnected to a high power potential (VBH) and the other terminalconnected to an input terminal b1 of the operational amplifier (OP1)1102. The resistor R4 has one terminal connected to the input terminalb1 of the operational amplifier (OP1) 1102 and the other terminalconnected to the low power potential (GND). A potential of the outputterminal c1 of the operational amplifier (OP1) 1102 is outputted as thelow power potential (VBL). The low power potential (VBL) corresponds toa difference between the high power potential (VBH) and the high powerpotential (V1).

FIG. 4A shows a light emitting device using the potential generatingcircuit shown in FIG. 3. In FIGS. 4A and 4B, the same reference numeralsas those in FIGS. 9, 2A, and 2B denote the same components. Further, thelight emitting device of this embodiment mode is similar to FIGS. 2A and2B of Embodiment Mode 1 except for a potential generating circuit 1101.

The potential generating circuit 1101 of this embodiment mode, is formedby using TFTs over the same substrate 500 as the pixel portion 501, thesource signal line driver circuit 502, and the gate signal line drivercircuit 503.

In the potential generating circuit 1101 as shown in FIG. 4B, two powersource connecting terminals of the operational amplifier (OP1) 1102 areconnected to the high power potential (VDD1) and the low power potential(GND) respectively. The output terminal c1 of the operational amplifier(OP1) 1102 is connected to the one terminal of the resistor R2 and thesignal line (the power source line) 1104 which supplies the low powerpotential (VBL) to the buffer group circuit 508.

The resistor R1 has one terminal connected to the signal line (the powersource line) 1105 which supplies the high power potential (V1) and theother terminal connected to the input terminal al of the operationalamplifier (OP1) 1102. The resistor R2 has one terminal connected to theinput terminal al of the operational amplifier (OP1) 1102 and the otherterminal connected to the output terminal c1 of the operationalamplifier (OP1) 1102. The resistor R3 has one terminal connected to thesignal line (the power source line) 1103 which supplies the high powerpotential (VBH) of the buffer and the light emitting element high powerpotential (ANODE) and the other terminal connected to the input terminalb1 of the operational amplifier (OP1) 1102. The resistor R4 has oneterminal connected to the input terminal b1 of the operational amplifier(OP1) 1102 and the other terminal connected to the low power potential(GND).

Here, an amplifier ratio of the operational amplifier (OP1) 1102 is 1and resistance of the resistors R1 to R4 are all equal. It is needlessto say that the resistance of the resistors Ri to R4 may be changed asrequired so as to set the buffer high power source potential (VBH), thelight emitting element high power potential (ANODE), the buffer lowpower potential (VBL), and the high power potential (V1) at the requiredlevels. Further, the operational amplifier (OP1) 1102 is preferablydesigned to consume less power.

The buffer group circuit 508 is connected to the signal lines 1103 and1104. The signal line 1103 is connected to the signal line 602 whichsupplies the buffer high power potential (VBH) of the buffer groupcircuit 508 and the signal line 1104 is connected to the signal line 603which supplies the buffer low power potential (VBL) (see FIG. 10B ). Asa result, the buffer high power potential (VBH) is supplied from thesignal line 1103 and the buffer low power potential (VBL) is suppliedfrom the signal line 1104.

In the pixel portion 501, a power supply line for supplying power to ananode of the light emitting element is provided. The power supply lineis connected to an external power source which applies the buffer highpower potential (VBH). Therefore, the buffer high power potential (VBH)is equal to the light emitting element high power potential (ANODE) inthis embodiment mode. It is to be noted that the high power potential(VBH) of the buffer and the light emitting element high power potential(ANODE) may be at the same level or different external power sources maybe provided. Sharing the power source leads to the reduction in powerand the number of connecting portions.

The high power potential (V1) is at a lower level than the buffer highpower potential (VBH) and the light emitting element high powerpotential (ANODE). Further, the buffer high power potential (VBH) hereis at the same level as the light emitting element high power potential(ANODE), however, the buffer high power potential (VBH) may be at ahigher level than the light emitting element high power potential(ANODE).

By the potential generating circuit 1101, the buffer low power potential(VBL) becomes a potential obtained by subtracting the high powerpotential (V1) from the light emitting element high power potential(ANODE). Accordingly, even when the light emitting element high powerpotential (ANODE) rises, the buffer low power potential (VBL) can riseby following the light emitting element high power potential (ANODE).

In this embodiment mode, by forming the potential generating circuit1101 over the same substrate 500 as the pixel portion 501, the sourcesignal line driver circuit 502, and the gate signal line driver circuit503, the number of external components can be reduced. It is needless tosay that the potential generating circuit 1101 may be all formed of anIC and then mounted over the substrate 500, for example, by the COGmethod and the like.

In this embodiment mode, the source signal line driver circuit 502 andthe gate signal line driver circuit 503 as well as the pixel portion 501are formed by using TFTs, however, a portion or all of each circuit maybe formed of an IC and then mounted by the COG method or the TAB method.

In Embodiment Modes 1 and 2, in the case of providing in the pixelportion 501 a plurality of kinds of light emitting elements formed ofdifferent EL materials, such as an EL element which emits red (R) light,an EL element which emits green (G) light, and an EL element which emitsblue (B) light, it is preferable to set the light emitting element highpower potentials (ANODE) depending on the kinds of the light emittingelements such as R, G, and B. Therefore, it is preferable to provide thelight emitting element high power potential (ANODE) and the buffer lowpower potential (VBL) depending on the kinds of the light emittingelements.

EMBODIMENT MODE 3

As described in Embodiment Modes 1 and 2, the invention is preferablyapplied to an electronic device which is required to have a highresolution display portion as the invention can suppress powerconsumption of an EL display device and variations in luminance of thedisplay portion caused by the high resolution of the pixels. Examplesare a television device (a television, a television receiver), a camerasuch as a digital camera, and a digital video camera, a portable phonedevice (a portable phone), a portable information terminal such as aPDA, a portable game machine, a monitor, a computer, an audioreproducing device such as a car audio set, and an image reproducingdevice provided with a recording medium such as a home game machine.Specific examples of these are described with reference to FIGS. 11A to11F.

For example, the invention can be applied to a portable informationterminal shown in FIG. 11A, a digital video camera shown in FIG. 11B, aportable phone shown in FIG. 11C, a portable television device shown inFIG. 11D, a notebook computer shown in FIG. 11E, and a television deviceshown in FIG. 11F. The invention can be used for display portions 2001to 2006 in each of the devices.

According to the invention, life of each of the devices shown in FIGS.11A to 11E with batteries can be prolonged as the power consumption isreduced.

In a large display portion such as the television device shown in FIG.11F also, heat generation of the source signal line driver circuit canbe suppressed, thereby variations in luminance caused by the generatedheat do not easily occur even when used for a long time.

EMBODIMENT Embodiment 1

In Embodiment 1, an example of manufacturing the light emitting deviceof Embodiment Mode 1 shown in FIGS. 2A and 2B is described. Thisembodiment is different than Embodiment Mode 1 in that the circuit inFIG. 1 employs an IC. FIG. 5 shows an equivalent circuit configurationof a pixel portion of this embodiment. A pixel configuration of thisembodiment is not limited to the circuit shown in FIG. 5.

As shown in FIG. 5, a source signal line 112 is connected to a sourceterminal of an n-channel TFT 120 of which drain terminal is connected toa source terminal of an n-channel TFT 117. Gate terminals of then-channel TFT 120 and the n-channel TFT 117 are connected to a gatesignal line 114. The n-channel TFT 120 and the n-channel TFT 117 areshown as two TFTs connected in series. However, the two n-channel TFTs117 and 120 are manufactured as one double gate TFT which shares asemiconductor layer provided with a channel.

A pixel capacitor Cp 116 has one terminal connected to a signal line (apower source line) 113 which applies the light emitting element highpower potential (ANODE) and the other terminal connected to a drainterminal of the n-channel TFT 117 and a gate terminal of a p-channel TFT118.

The p-channel TFT 118 has a source terminal connected to the signal line113 which applies the light emitting element high power potential(ANODE) and a drain terminal connected to an anode of a light emittingelement 119.

The light emitting element 119 is formed of an EL element of which anodeis connected to the drain terminal of the p-channel TFT 118 and of whichcathode is connected to a light emitting element low power potential(CATHODE).

FIGS. 6 and 7 show measurement results showing the effects of thisembodiment. Both of FIGS. 6 and 7 show data in the case where the bufferhigh power potential (VBH) is in synchronization with the light emittingelement high power potential (ANODE) so as to be at the same level.

FIG. 6 shows a change of the buffer low power potential (VBL) inaccordance with a change of the light emitting element high powerpotential (ANODE). FIG. 7 shows a change of a current flowing throughthe signal line 1004 which supplies the buffer low power potential (VBL)in accordance with a change of the light emitting element high powerpotential (ANODE). By setting the high power potential (VDD1) of theoperational amplifier (OP1) at 15 V and the low power potential (GND)thereof at 0 V, the light emitting element high power potential (ANODE)is changed from 5 to 12 V. The high power potential (V1) is set at 3, 4,and 5 V, thereby a light emitting device is driven in the digital grayscale by the line sequential method.

In FIG. 6, data of the buffer low power potential (VBL) fixed at 0 Vcorresponds to data of a light emitting device of a comparison examplewhich is not provided with the circuit shown in FIG. 1. The same can beapplied to the comparison examples in FIGS. 7, and 8B, and 8D.

As shown in FIG. 6, in a conventional configuration, the buffer lowpower potential (VBL) is fixed at 0 V. Therefore, a potential differencebetween the high power potential (VBH) and the low power potential(VBL), which are supplied to an inverter of the buffer is increased whenthe light emitting element high power potential (ANODE) rises.

In this embodiment, on the other hand, the buffer low power potential(VBL) rises by following the rise of the light emitting element highpower potential (ANODE), thereby a potential difference between the highpower potential (VBH) and the low power potential (VBL) is decreased ascompared to the comparison example as shown in FIG. 6.

It is found in FIG. 7 that a current value is in proportion to the lightemitting element high power potential (ANODE) in the case where thebuffer low power potential (VBL) is fixed in the display device of thecomparison example, and that the current value is increased as the lightemitting element high power potential (ANODE) rises.

In this embodiment, on the other hand, the current value is not inproportion to the rise of the light emitting element high powerpotential (ANODE). In the case where the light emitting element highpower potential (ANODE) is 7 V or higher, the current value is about 5.6mA when the buffer low power potential (VBL) is 3 V, about 7 mA when thebuffer low power potential is 4 V, and about 9 mA when the buffer lowpower potential is 5 V, and thus the current values can be seen to bealmost constant.

That is, in accordance with this embodiment, rise in power consumptioncan be suppressed even when the light emitting element high powerpotential (ANODE) rises depending on a change over time and atemperature. Further, heat generation of the source signal line circuitcan be suppressed.

A temperature of a source signal line driver circuit and luminance of apixel portion of a light emitting device are measured after one hour ofdriving in order to further check the effects of this embodiment. FIGS.8A and 8B show temperatures of the source signal line of this embodimentand the comparison example respectively. FIGS. 8C and 8D show luminanceof the light emitting element of this embodiment and the comparisonexample respectively. The light emitting device of this embodiment isdriven by fixing the light emitting element high power potential (ANODE)at 10 V and the high power potential (V1) at 4 V respectively. The lightemitting device of the comparison example is measured by fixing thelight emitting element high power potential (ANODE) at 10 V.

As shown in FIGS. 8A and 8B, the temperature of the source signal linedriver circuit is lower in the light emitting device of this embodimentthan the comparison example. This embodiment of (A) has an averagetemperature lower than the comparison example (B) by about 5° C. Thedeterioration in luminance caused by an environment temperature isaffected by the change of 2 to 3° C., therefore, the fall of 5° C. ofthis invention is considered a large effect. That is, heat generation issuppressed and variations in luminance caused by the generated heat canbe suppressed by this embodiment.

In the embodiment shown in FIG. 8C, heat generation of the source signalline driver circuit is suppressed, therefore, luminance is almost equalin the periphery of the source signal line driver circuit and theperiphery of the center of the pixel portion. However, in FIG. 8D, theluminance of a portion on the source signal line driver circuit side isincreased by the generated heat of the source signal line drivercircuit, and thus variations in luminance are caused. That is,variations in luminance of the pixel portion caused by the generatedheat are suppressed by this embodiment.

In this embodiment, an effect of the circuit of Embodiment Mode 1 isverified. It is easily estimated by the aforementioned experimentresults that a similar effect can be obtained by the circuit ofEmbodiment Mode 2.

This application is based on Japanese Patent Application serial no.2004-339684 filed in Japan Patent Office on 24 Nov. 2004, the entirecontents of which are hereby incorporated by reference.

1. A light emitting device comprising: a light emitting element, abipolar transistor, an operational amplifier, a driver circuit, a firstresistor, a second resistor, a third resistor, and a fourth resistor,wherein the bipolar transistor has a base terminal connected to anoutput terminal of the operational amplifier and a collector terminalconnected to a low power potential, wherein the first resistor has oneterminal connected to a first high power potential and the otherterminal connected to a first input terminal of the operationalamplifier, wherein the second resistor has one terminal connected to thefirst input terminal of the operational amplifier and the other terminalconnected to the emitter terminal of the bipolar transistor, wherein thethird resistor has one terminal connected to the second high powerpotential and the other terminal connected to a second input terminal ofthe operational amplifier, wherein the fourth resistor has one terminalconnected to a second input terminal of the operational amplifier andthe other terminal connected to a low power potential, wherein apotential from the emitter terminal of the bipolar transistor and theother terminal of the second resistor is supplied as a low powerpotential of a buffer of the driver circuit, and wherein the second highpower potential is supplied as a high power potential of the buffer. 2.The light emitting device according to claim 1, wherein the lightemitting element is an EL element.
 3. The light emitting deviceaccording to claim 1, wherein the light emitting device is provided overa semiconductor substrate.
 4. The light emitting device according toclaim 1, wherein the light emitting device is provided over a glasssubstrate.
 5. The light emitting device according to claim 1, whereinthe light emitting device is provided over a flexible substrate.
 6. Thelight emitting device according to claim 1, wherein the light emittingdevice is provided over an SOI substrate.
 7. The light emitting deviceaccording to claim 1, wherein the light emitting device includes a thinfilm transistor.
 8. An IC card, an IC tag, an RFID, a transponder, papermoney, securities, a passport, an electronic device, a bag, clothes eachof which includes the light emitting device according to claim
 1. 9. Alight emitting device comprising: a light emitting element, anoperational amplifier, a driver circuit, a first resistor, a secondresistor, a third resistor, and a fourth resistor, wherein the firstresistor has one terminal connected to a first high power potential andthe other terminal connected to a first input terminal of theoperational amplifier, wherein the second resistor has one terminalconnected to the first input terminal of the operational amplifier andthe other terminal connected to an output terminal of the operationalamplifier, wherein the third resistor has one terminal connected to asecond high power potential and the other terminal connected to a secondinput terminal of the operational amplifier, wherein the fourth resistorhas one terminal connected to the second input terminal of theoperational amplifier and the other terminal connected to a low powerpotential, wherein a potential of the other terminal of the secondresistor is supplied as a lower power potential of a buffer, and whereinthe second high power potential is supplied as a higher power potentialof the buffer.
 10. The light emitting device according to claim 9,wherein the light emitting element is an EL element.
 11. The lightemitting device according to claim 9, wherein the light emitting deviceis provided over a semiconductor substrate.
 12. The light emittingdevice according to claim 9, wherein the light emitting device isprovided over a glass substrate.
 13. The light emitting device accordingto claim 9, wherein the light emitting device is provided over aflexible substrate.
 14. The light emitting device according to claim 9,wherein the light emitting device is provided over an SOI substrate. 15.The light emitting device according to claim 9, wherein the lightemitting device includes a thin film transistor.
 16. An IC card, an ICtag, an RFID, a transponder, paper money, securities, a passport, anelectronic device, a bag, clothes each of which includes the lightemitting device according to claim
 9. 17. A light emitting devicecomprising: a bipolar transistor having a base terminal, and a collectorterminal and an emitter terminal; a circuit having an operationalamplifier, a first resistor, a second resistor, a third resistor, afourth resistor; and a driver circuit having a buffer, wherein theoperational amplifier has an output terminal, a first input terminal anda second input terminal, wherein the base terminal is connected to theoutput terminal of the operational amplifier and the collector terminalis connected to a low power potential, wherein the first resistor hasone terminal connected to a first high power potential and the otherterminal connected to the first input terminal of the operationalamplifier, wherein the second resistor has one terminal connected to thefirst input terminal of the operational amplifier and the other terminalconnected to the emitter terminal of the bipolar transistor, wherein thethird resistor has one terminal connected to a second high powerpotential and the other terminal connected to the second input terminalof the operational amplifier, wherein the fourth resistor has oneterminal connected to the second input terminal of the operationalamplifier and the other terminal connected to a low power potential,wherein a potential from the emitter terminal of the bipolar transistorand the other terminal of the second resistor is equal to a low powerpotential of the buffer of the driver circuit, and wherein the secondhigh power potential is equal to as a high power potential of thebuffer.
 18. The light emitting device according to claim 17, wherein thelight emitting device is provided over a semiconductor substrate. 19.The light emitting device according to claim 17, wherein the lightemitting device is provided over a glass substrate.
 20. The lightemitting device according to claim 17, wherein the light emitting deviceis provided over a flexible substrate,
 21. The light emitting deviceaccording to claim 17, wherein the light emitting device is providedover an SOI substrate.
 22. The light emitting device according to claim17, wherein the light emitting device includes a thin film transistor.23. An IC card, an IC tag, an RFID, a transponder, paper money,securities, a passport, an electronic device, a bag, clothes each ofwhich includes the light emitting device according to claim
 17. 24. Alight emitting device comprising: a circuit having an operationalamplifier, a first resistor, a second resistor, a third resistor, afourth resistor; and a driver circuit having a buffer, wherein theoperational amplifier has an output terminal, a first input terminal anda second input terminal, wherein the first resistor has one terminalconnected to a first high power potential and the other terminalconnected to the first input terminal of the operational amplifier,wherein the second resistor has one terminal connected to the firstinput terminal of the operational amplifier and the other terminalconnected to the output terminal of the operational amplifier, whereinthe third resistor has one terminal connected to a second high powerpotential and the other terminal connected to the second input terminalof the operational amplifier, wherein the fourth resistor has oneterminal connected to the second input terminal of the operationalamplifier and the other terminal connected to a low power potential,wherein a potential of the other terminal of the second resistor isequal to a lower power potential of a buffer, and wherein the secondhigh power potential is equal to as a higher power potential of thebuffer.
 25. The light emitting device according to claim 24, wherein thelight emitting device is provided over a semiconductor substrate. 26.The light emitting device according to claim 24, wherein the lightemitting device is provided over a glass substrate.
 27. The lightemitting device according to claim 24, wherein the light emitting deviceis provided over a flexible substrate.
 28. The light emitting deviceaccording to claim 24, wherein the light emitting device is providedover an SOI substrate.
 29. The light emitting device according to claim24, wherein the light emitting device includes a thin film transistor.30. An IC card, an IC tag, an RFID, a transponder, paper money,securities, a passport, an electronic device, a bag, clothes each ofwhich includes the light emitting device according to claim
 24. 31. Adriving method of a light emitting device comprising a buffer, thedriving method comprising the steps of: supplying a high power potentialto the buffer; and supplying a low power potential to the buffer,wherein, when the high power potential rises, the low power potentialrises by following the rising of the high power potential.